Tutorials & Invited | CHIP on the sands 2017

Tutorials & Invited

Keynotes Speakers

Self-Aware Silicon

Axel Jantsch


Self-awareness describes the capability of a system to monitor its own state, its performance and its integrity. A system on chip, that is equipped with an accurate assessment of its own situation, is in a strong position to manage its resources, prioritize its goals, identify and counteract aberrations in its behavior due to aging, faulty hardware, ill designed software or malicious attacks. This talk will survey the state of the art of the field and highlight the benefits of self-awareness for systems on chip.

Short Bio:

Axel Jantsch received the Dipl.Ing. and Dr. Tech. degrees from TU Wien, Vienna, Austria, in 1988 and 1992, respectively. He was with Siemens Austria, Vienna, Austria, as a system validation engineer from 1995 to 1997. From 1997to 2002 he was an associate professor and from 2002 to 2014 he was full professor of Electronic Systems Design at the Royal Institute of Technology (KTH), Stockholm, Sweden. Since 2014 he has been professor of Systems on Chip at TU Wien. He has published about 300 papers in international conferences and journals and one book in the areas of Systems on chip, networks on chip and embedded systems. He has served on a large number of technical program committees of international conferences, such as FDL, DATE, CODES ISSS, SOC, NOCS, and others. He has been the TPC Chair of SSDL/ FDL 2000, the TPC Co-Chair of CODES ISSS 2004, the General Chair of CODES ISSS 2005, and the TPC Co-Chair of NOCS 2009. From 2002 to 2007, he was a subject area editor for the Journal of System Architecture. He is on the editorial board for IEEE Design and Test and for the Leibniz Transactions on Embedded Systems. He is a member of the IEEE. His main research interest is on networks on chip and self-awareness in systems on chip and embedded systems.

Designing Energy-Efficient Many-Core Servers for Exascale Computing

David Atienza Alonso


Continuous advances in manufacturing technologies are enabling the development of more powerful and compact high-performance computing (HPC) servers made of many-core processing architectures. However, this soaring demand for computing power in the last years has grown faster than semiconductor technology evolution can sustain, and has produced as collateral undesirable effect a surge in power consumption and heat density in these new HPC servers, which result on significant performance degradation. In this keynote, I advocate to completely revise the current HPC server architectures. In particular, inspired by the mammalian brain, I propose to design a disruptive three-dimensional (3D) computing server architecture that overcomes the prevailing worst-case power and cooling provisioning paradigm for servers. This new 3D server design champions a new system-level thermal modeling, which can be used by novel proactive energy controllers for detailed heat and energy management in many-core HPC servers, thanks to micro-scale liquid cooling. Then, I will show the impact of new near-threshold computing architectures on server design, and how we can integrate new on-chip microfluidic fuel cell networks to enable energy- scalability in future generations of many-core HPC servers targeting Exascale computing.

Short Bio:

David Atienza is Associate Professor of Electrical and Computer Engineering and Director of the Embedded Systems Laboratory (ESL) at EPFL, Switzerland. He received his MSc and PhD degrees in Computer Science and Engineering from UCM (Spain) and IMEC (Belgium). His research interests focus on system-level design methodologies for energy-efficient multi- processor system-on- chip architectures (MPSoC) and next-generation embedded systems. In these fields, he is co-author of more than 250 publications, seven patents, and received several best paper awards in top conferences. He was the Technical Program Chair of DATE 2015 and General Chair of DATE 2017. He received an ERC Consolidator Grant in 2016, the IEEE CEDA Early Career Award in 2013, the ACM SIGDA Outstanding New Faculty Award in 2012, and a Faculty Award from Sun Labs at Oracle in 2011. He was Distinguished Lecturer of IEEE CASS in 2014 and 2015. He is a senior member of ACM and an IEEE Fellow.